
#ifndef __DAVINCI_SPI1_H
#define __DAVINCI_SPI1_H

#define DAVINCI_SPI1_BASE           (0x01C66800)

typedef	struct  {
	volatile unsigned int SPIGCR0;
	volatile unsigned int SPIGCR1;
	volatile unsigned int SPIINT;
	volatile unsigned int SPILVL;
	volatile unsigned int SPIFLG;
	volatile unsigned int SPIPC0;
	volatile unsigned int SPIPC1;
	volatile unsigned int SPIPC2;
	volatile unsigned int SPIPC3;
	volatile unsigned int SPIPC4;
	volatile unsigned int SPIPC5;
	volatile unsigned int SPIPC6;
	volatile unsigned int SPIPC7;
	volatile unsigned int SPIPC8; 	
	volatile unsigned int SPIDAT0;
	volatile unsigned int SPIDAT1;
	volatile unsigned int SPIBUF;
	volatile unsigned int SPIEMU;
	volatile unsigned int SPIDELAY;
	volatile unsigned int SPIDEF;
	volatile unsigned int SPIFMT[4];
	//volatile unsigned int TGINTVEC[2];
	volatile unsigned int INTVECT0;
	volatile unsigned int INTVECT1;
//	volatile unsigned int MIBSPIE;
}davinci_spi_reg;



/* SPI Controller registers */
/*#define SPIGCR0		0x00
#define SPIGCR1		0x04
#define SPIINT		0x08
#define SPILVL		0x0c
#define SPIFLG		0x10
#define SPIPC0		0x14
#define SPIPC1		0x18
#define SPIPC2		0x1c
#define SPIPC3		0x20
#define SPIPC4		0x24
#define SPIPC5		0x28
#define SPIPC6		0x2c
#define SPIPC7		0x30
#define SPIPC8		0x34
#define SPIDAT0		0x38
#define SPIDAT1		0x3c
#define SPIBUF		0x40
#define SPIEMU		0x44
#define SPIDELAY	0x48
#define SPIDEF		0x4c
#define SPIFMT0		0x50
#define SPIFMT1		0x54
#define SPIFMT2		0x58
#define SPIFMT3		0x5c
#define TGINTVEC0	0x60
#define TGINTVEC1	0x64
*/
/*
struct davinci_spi1_dma {
	int			dma_tx_channel;
	int			dma_rx_channel;
	int			dma_tx_sync_dev;
	int			dma_rx_sync_dev;
	enum dma_event_q	eventq;
};*/

typedef	struct{
	void*		virtAddr;
	void*		physAddr;
}SPIBuf,*PSPIBuf;

typedef	struct{
	int			nNum;
	int			nSize;
	PSPIBuf		spi_buf_ptr;
}SPIBufInfo;

/*  ioctl option  */
enum{
	SPI_GET_BUFINFO = 0,
	SPI_GET_BUFDETAIL,
	SPI_LOCK_BUF,
	SPI_UNLOCK_BUF,
	SPI_STREAM_ON,
	SPI_STREAM_OFF,
	FPGA_REST
};
typedef struct {
	unsigned int er;
	unsigned int erh;
	unsigned int ecr;
	unsigned int ecrh;
	unsigned int esr;
	unsigned int esrh;
	unsigned int cer;
	unsigned int cerh;
	unsigned int eer;
	unsigned int eerh;
	unsigned int eecr;
	unsigned int eecrh;
	unsigned int eesr;
	unsigned int eesrh;
	unsigned int ser;
	unsigned int serh;
	unsigned int secr;
	unsigned int secrh;
	unsigned char rsvd0[8];
	unsigned int ier;
	unsigned int ierh;
	unsigned int iecr;
	unsigned int iecrh;
	unsigned int iesr;
	unsigned int iesrh;
	unsigned int ipr;
	unsigned int iprh;
	unsigned int icr;
	unsigned int icrh;
	unsigned int ieval;
	unsigned char rsvd1[4];
	unsigned int qer;
	unsigned int qeer;
	unsigned int qeecr;
	unsigned int qeesr;
	unsigned int qser;
	unsigned int qsecr;
	unsigned char rsvd2[360];
} edmacc_shadow_regs;
typedef struct {
	unsigned int drae;
	unsigned int draeh;
} edmacc_dra_regs;
typedef struct {
	unsigned int evt_entry;
} edmacc_que_evtentry_regs;
typedef struct {
	unsigned int opt;
	unsigned int src;
	unsigned int a_b_cnt;
	unsigned int dst;
	unsigned int src_dst_bidx;
	unsigned int link_bcntrld;
	unsigned int src_dst_cidx;
	unsigned int ccnt;
} edmacc_paramentry_regs;

typedef struct {
	unsigned int rev;
	unsigned int cccfg;
	unsigned char rsvd0[244];
	unsigned int clkgdis;
	unsigned int dchmap[64];
	unsigned int qchmap[8];
	unsigned char rsvd1[32];
	unsigned int dmaqnum[8];
	unsigned int qdmaqnum;
	unsigned char rsvd2[28];
	unsigned int quetcmap;
	unsigned int quepri;
	unsigned char rsvd3[120];
	unsigned int emr;
	unsigned int emrh;
	unsigned int emcr;
	unsigned int emcrh;
	unsigned int qemr;
	unsigned int qemcr;
	unsigned int ccerr;
	unsigned int ccerrclr;
	unsigned int eeval;
	unsigned char rsvd4[28];
	edmacc_dra_regs dra[8];
	unsigned int qrae[8];
	unsigned char rsvd5[96];
	edmacc_que_evtentry_regs queevtentry[8][16];
	unsigned int qstat[8];
	unsigned int qwmthra;
	unsigned int qwmthrb;
	unsigned char rsvd6[24];
	unsigned int ccstat;
	unsigned char rsvd7[188];
	unsigned int aetctl;
	unsigned int aetstat;
	unsigned int aetcmd;
	unsigned char rsvd8[244];
	unsigned int mpfar;
	unsigned int mpfsr;
	unsigned int mpfcr;
	unsigned int mppag;
	unsigned int mppa[8];
	unsigned char rsvd9[2000];
	unsigned int er;
	unsigned int erh;
	unsigned int ecr;
	unsigned int ecrh;
	unsigned int esr;
	unsigned int esrh;
	unsigned int cer;
	unsigned int cerh;
	unsigned int eer;
	unsigned int eerh;
	unsigned int eecr;
	unsigned int eecrh;
	unsigned int eesr;
	unsigned int eesrh;
	unsigned int ser;
	unsigned int serh;
	unsigned int secr;
	unsigned int secrh;
	unsigned char rsvd10[8];
	unsigned int ier;
	unsigned int ierh;
	unsigned int iecr;
	unsigned int iecrh;
	unsigned int iesr;
	unsigned int iesrh;
	unsigned int ipr;
	unsigned int iprh;
	unsigned int icr;
	unsigned int icrh;
	unsigned int ieval;
	unsigned char rsvd11[4];
	unsigned int qer;
	unsigned int qeer;
	unsigned int qeecr;
	unsigned int qeesr;
	unsigned int qser;
	unsigned int qsecr;
	unsigned char rsvd12[3944];
	edmacc_shadow_regs shadow[8];
	unsigned char rsvd13[4096];
	edmacc_paramentry_regs paramentry[512];
} edmacc_regs;

extern void davinci_spi1_modeset();

#endif

